1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device having memory cells for storing data in capacitors as well as redundant memory cells to be used for replacing a defective memory cell.
2. Description of the Background Art
In a field of data processing and others, circuit devices, which are referred to as xe2x80x9csystem LSIs (Large Scale Integrated Circuits)xe2x80x9d have been widely used for fast data processing with low power consumption. In the system LSI, a logic such as a processor and a memory device are integrated on a common semiconductor chip. Since the logic and the memory device are mutually connected via on-chip interconnections, the system LSI can achieve the following advantages. (1) A load on a signal interconnection is smaller than that on an on-board interconnection so that data/signal can be transmitted fast. (2) Since there is no restriction on the number of pins, data bits can be increased in number so that a band width of data transfer can be increased. (3) Since respective components are integrated on the semiconductor chip to a higher extent than a structure, in which elements are individually arranged on a board, a system scale can be small, and the size and weight of the system can be small. (4) Since macros contained in library can be arranged as components to be formed on the semiconductor ship, this improves the design efficiency.
For the reasons described above, the system LSIs have been widely used in various fields, and memories such as DRAMs (Dynamic Random Access Memories), SRAMs (Static Random Access Memories) and flash EEPROMs (Electrically Erasable and Programmable Read Only Memories) are used as the integrated memory devices. Also, the logics are formed of processors performing control and processing, analog processing circuits such as A/D converter circuits, and/or dedicated logic circuits performing logical processing.
For integrating the processor and memory device in the system LSI, it is necessary to form the logic and the memory device in the same manufacturing steps as far as possible for reducing the number of manufacturing steps and therefore the cost. The DRAM stores data taking the form of electric charges in the capacitor. The capacitor has electrodes, which are referred to as a cell plate electrode and a storage node electrode, respectively, and are located at an upper portion of a semiconductor substrate region.
The above capacitor structure has a complicated form such as a hollow and cylindrical form for providing a large capacitance with a small occupied area. Accordingly, even if a DRAM-logic merging process for forming the DRAM and the logic in the same manufacturing process is employed, and the transistors of the logic and the transistors of the DRAM are formed in the same manufacturing step, it is necessary to provide a step of forming the capacitor of the DRAM, and it is also necessary to provide a flattening process for reducing a difference in level, which is formed between the DRAM and the logic due to a three-dimensional structure of the capacitor of the DRAM or between the DRAM memory array and its peripheral portion. Consequently, the manufacturing steps increase significantly in number, which increases the chip cost.
In an SRAM, each memory cell is formed of four transistors and two load elements. These load elements are usually formed of MOS transistors (insulated gate field-effect transistors), and do not employ a capacitor or the like. Therefore, the SRAM can be formed in a complete CMOS logic process. Thus, the SRAM and the logic can be formed in the same manufacturing process. The SRAMs have been used as cache memories, register file memories and others for the processors because they can operate fast.
In the SRAM, the memory cell is formed of a flip-flop circuit, and keeps data as long as it is supplied with a power supply voltage. Therefore, the SRAM does not require refreshing for holding the data in contrast to the DRAM. In the portable information terminals or the like, therefore, the SRAMs have been widely used as main memories for simplifying the system structures because the SRAM does not require complicated memory control for refreshing, which is essential in the DRAM, and can be controlled more simply than the DRAM.
Even in the portable information terminals, however, it is now necessary to handle large amounts of data such as audio data and/or image data as a result of recent improvement of functions, and therefore memories of large storage capacities are required.
Owing to development of fine work process, the memory size of the DRAM has been shrunk, and a cell size of 0.3 square micrometers has been achieved in a 0.18-xcexcm DRAM process. In the SRAM, a full CMOS memory cell is formed of six MOS transistors including two P-channel MOS transistors and four N-channel MOS transistors.
Accordingly, even if the shrinking process has been developed, it is necessary to separate an N-well for forming the P-channel MOS transistor in the memory cell from a P-well for forming the N-channel MOS transistor. Due to the restrictions on the separation distance between the wells and others, the memory size of the SRAM has been shrunk only to a smaller extent than the DRAM. For example, the memory size of the SRAM in the 0.18-xcexcm CMOS logic process is substantially equal to 7 square micrometers, and thus is larger by 20 times than the memory size of the DRAM.
Accordingly, in the case of utilizing the SRAM as the main memory of a large storage capacity, the chip size significantly increases, and therefore it is extremely difficult to arrange the SRAM of the storage capacity of 4 Mbits or more together with the logic in the system LSI having a restricted chip area.
Accordingly, an object of the invention is to provide a semiconductor memory device, in which a large storage capacity can be achieved with a small occupied area without significantly increasing the number of manufacturing steps, and particularly a structure for suppressing wasteful power consumption.
A semiconductor memory device according to the invention includes a plurality of memory cells arranged in rows and columns, and each including a capacitor having a cell plate electrode receiving a reference voltage and a storage electrode for accumulating charges corresponding to storage information; a plurality of word lines arranged corresponding to the plurality of rows of the memory cells, respectively, and each connected to the memory cells in the corresponding row; a row select circuit for setting each of the plurality of word lines to one of voltages corresponding to an active state and an inactive state, respectively, in accordance with an address signal; a plurality of bit lines arranged corresponding to the plurality of columns of the memory cells, respectively, and each connected to the memory cells in the corresponding column; a plurality of cell plate electrode lines formed at the same interconnection layer as the plurality of word lines, and each arranged for a predetermined number of rows for being commonly used as the cell plate electrode by the plurality of memory cells corresponding to a predetermined number of rows; a cell plate voltage line for supplying the reference voltage; and a plurality of power-off control portions each arranged for the cell plate electrode lines of N (N: natural number) in number corresponding to a redundant replacement unit for a faulty row for stopping supply of the reference voltage from the cell plate voltage line to the corresponding N cell plate electrode lines in accordance with an instruction.
Preferably, each of the power-off control portions includes a program element electrically coupled between the cell plate voltage line and the corresponding N cell plate electrode lines. The program element nonvolatilely changes from an on state to an off state in response to the instruction supplied when the corresponding redundant replacement unit contains the faulty row.
In the above structure, the program element is formed of a fuse element.
Preferably, N is equal to one, and the redundant replacement unit is formed of at least one row corresponding to the same cell plate electrode line.
In the semiconductor memory device described above, the redundant replacement unit for the faulty row is set corresponding to the cell plate electrode line, and the supply of the reference voltage (cell plate voltage) to the cell plate electrode line can be stopped for each redundant replacement unit for the faulty line. As a result, the cell plate electrode line and the word line are formed at the same interconnection layer so that the manufacturing steps can be simple. Also, a large storage capacity can be achieved with a small occupied area. Further, manufacturing yield can be stably kept by redundant repair. At the same time, it is possible to avoid increase in current consumption due to short-circuit between the cell plate electrode line and the word line.
Preferably, the plurality of word lines include sub-word lines arranged for the rows, respectively, and main word lines each provided for the rows of M (M: integer larger than one) in number and arranged hierarchically with respect to the sub-word line. The rows corresponding to the cell plate electrode lines of N in number belonging to the same redundant replacement unit are related to the same main word line.
As a result, the power-off control portions can be efficiently reduced in number in the hierarchical word line structure.
Alternatively, each of the power-off control portions may preferably include a latch circuit for holding a control signal indicating whether the corresponding redundant replacement unit contains the faulty row or not, and a first power supply switch electrically coupled between the cell plate voltage line and the corresponding N cell plate electrode lines for being turned on/off in response to the control signal held in the latch circuit.
According to the above structure, it is not necessary to arrange, for each cell plate electrode line, a program element for cutting off the power.
Further, each of the power-off control portions may preferably include a second power supply switch electrically coupled between the voltage corresponding to the inactive state of each word line and the N cell plate electrode lines for being turned on complementarily with the first power supply switch in response to the control signal held in the latch circuit.
Thereby, it is possible to prevent further reliably the occurrence of a leak current from a short-circuited path between the cell plate electrode line and the word line.
Preferably, the semiconductor memory device further includes an address determining circuit for storing a faulty address indicating the redundant replacement unit including the faulty row, and successively producing the control signal for each of the redundant replacement units based on comparison between each of the successively renewed address signals and the faulty address. Each of the power-off control portions further includes a gate circuit for transmitting the control signal received from the address determining circuit to the latch circuit when the successively renewed address signal indicates the corresponding redundant replacement unit. The latch circuit holds the control signal transmitted by the gate circuit during the power-on state.
As a result, the address determining circuit, which is required for redundant replacement repair, can be commonly used when executing the power supply control for the cell plate electrode lines. For a predetermined period starting from the power-on, it is determined whether each of the cell plate electrode lines is to be replaced or not, and the power supply to the cell plate electrode line is fixedly executed during a subsequent power-on period. Therefore, no adverse effect is exerted on the normal memory operation.
Preferably, the cell plate voltage line includes a plurality of interconnections capable of externally receiving independent voltages, respectively, during an operation test.
Alternatively, the cell plate voltage line may include two interconnections capable of externally receiving independent voltages, respectively, during an operation test. The neighboring two lines among the plurality of cell plate voltage lines are connected to the two interconnections via the corresponding power-off control portions.
According to the above structure, a burn-in test can be effectively executed for screening a faulty portion hiding in an insulating film located between the cell plate electrode line and the word line, which are formed at the same interconnection layer.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.